One feature of a heterojunction is that the bandgaps of two adjacent semiconductors are typically different. As a result the energy of the carriers (electrons or holes) that exists at at least one of the band edges must change as the carriers pass through the heterojunction. In most cases the discontinuities exist in both the conduction band and the valence band. In conventional nomenclature, sometimes used with superlattices, if the extrema of both the conduction and valence bands lie in the same layers, the superlattice is referred to as Type I, whereas if the band extrema are found in different layers the superlattice is referred to as Type II.
The FinFET is becoming a main architecture for CMOS technology due to its excellent scalability. However FinFET circuit design is challenging due at least to the discrete values that are available for W (the effective device width). For example, if the fin height is 30 nm and W is equal to two times the height (H) of the fin or 60 nm, and if a circuit designer desires a value of W equal to 90 nm, the circuit designer should either use one fin with W equal to 60 nm or two fins with a total W equal to 120 nm. Moreover the effective device width for various chip blocks such as SRAM and logic are typically similar. It can be appreciated that constraints can be placed on the circuit designer.